FreeRTOS v8.2.0 for Cadence Tensilica Xtensa processors (v1.4.2)

This contributed kernel port and demo/test suite is for all Cadence Tensilica Xtensa processors.  To install, extract the files onto the directory where you have already extracted FreeRTOS.  You can find the makefile and readme in the <FreeRTOS>/Demo/Xtensa_XCC directory.  Build it using xt-make (included in the command line tools in the SDK available from Cadence).  The build can be targeted to run on the simulator included in the SDK, or on several Xilinx FPGA boards.  For more information about Xtensa processors, including a link to request a trial SDK, go to http://ip.cadence.com/ipportfolio/tensilica-ip or contact your local Cadence sales representative.

This port was developed by Nestwave (contact [_at_] nestwave.com)



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