FreeRTOS 8.2.3 for MIPS32 processor cores

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FreeRTOS-8.2.3-mips32-18Jan2016.zip
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This port provides support for MIPS32 cores.


Requirements:

This port is dependent on features provided by Codescape SDK.
To get the latest version visit the following website:

http://community.imgtec.com/developers/mips/tools/codescape-mips-sd...

You must use SDK v1.3 or higher.

Or if you're just installing the tools on their own, it must be v2015.06-xx
or higher.

You will also need FreeRTOS-8.2.3 official release which this release must be extracted on top of.


Features:
   * Vectored interrupt, GIC and EIC support.
   * Count/Compare register based internal timer support.
   * DSP and FPU context switching.

New Changes:

Context saving amended:

The DSP and FPU contexts where overwriting the normal context. They are now saved after the normal context.

A new demo added:

A demo using lwIP-1.4.1 has been added. It uses interrupts for the Ethernet and Uart devices available on a ci40 mips target board. There is also a graph plotting scheme, where a freeRTOS task on the target, controlled by an inter-processor interrupt, will produce data that can be visualized in the Codescape debugger by the use of a script plot_results.py, that can be found with the demo's directory

Interrupt Helper functions:

Helper functions have been added which can be used when setting non EIC vectored interrupts.

GIC base address:

The ability to specify a base address for the GIC has been added

Building the Demo(for a ci40 target):
   * ARCH=interaptiv INTS=eic GIC_BASE_ADDRESS=0x1BDC0000 make

NOTE: The compiler must be in your path. You'll need mips-mti-elf- toolchain
for mips32r2-r5 targets and mips-img-elf- for mips32r6 targets.