FreeRTOS 8.1.2 for MIPS32 processor cores

This is an initial port of FreeRTOS 8.1.2 for MIPS32 processor cores.


  • Baseline (Release 1 compatibility) mode interrupt support, with vector interrupts and external interrupt controller support currently in development;
  • Count/Compare register based internal timer support; and,
  • MIPS32 code and exception handling, microMIPS code and exception handling, or a mixture of both. MIPS32 and microMIPS exception handlers are mutually exclusive, but application code can be a mixture of both MIPS32 and microMIPS.


The port has been tested with the Codescape MIPS SDK (available for free at http://community.imgtec.com/developers/mips/tools/codescape-mips-sdk/ ), however any available GNU toolchain that has support for microMIPS code generation may be used. The demo application does require the use of the IASim instruction accurate simulator, which is only available with the Codescape MIPS proSDK. The demo may work on the free QEMU emulator, however this has not been tested.

Building the demo:

The demo is based upon the basic demo for the Kiel simulator, which creates two simple tasks: one send task, which posts a value to a queue; and one receive task, which consumes a value from the queue and ensures it is the same as the value sent. A counter variable is then incremented after each valid consumed value.

To build the demo, navigate to 'FreeRTOS/Demos/MIPS32_IASIM_GCC/' and then run 'make'. This will create a binary named 'RTOSDemo.elf'.

To build microMIPS code, add 'MICROMIPS=1' to the make command; to build the exception handlers in microMIPS mode, add 'MICROMIPS_EXCEPTIONS=1' to the make command.

To run the demo, access to Codescape Debugger and IASim is required (the debugger is required to monitor the incrementing variable due to an issue with console output). QEMU may be used, or GDB and its emulation layer, however these configurations have not been fully tested.

Coming soon:

  • Vectored interrupt (VI) and external interrupt controller (EIC) modes;
  • Global interrupt controller (GIC) support;
  • MIPS32 Revision 6 instruction set support;
  • MSA & FPU support;
  • MIPS DSP support; and,
  • SEAD-3 hardware support.

Any questions and comments will be greatly appreciated.





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