This is a modification of the ARM Cortex M3 MPU port of FreeRTOS.
FPU use within some or all tasks is supported.
The interrupt latency time in NOT affected as FPU context switching is done only on context switches from and to tasks that really use the FPU.
ISRs may also use the FPU but are responsible for saving and restoring all used FPU registers.
The modified FreeRTOS code can be browsed here: http://schaefer.eit.h-da.de/ARM/CORTEX_M4/FreeRTOS_MPU_plus_FPU_Port
A test program for the STM3240G-Eval board is documented here: http://schaefer.eit.h-da.de/ARM/CORTEX_M4/STM3240G_Eval_Testproject