SAM4S-EK_FreeRTOS+FAT-SL  1.0
An example project to test the functionality of FreeRTOS+FAT-SL using SD card as data storage medium
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HSMCI.c
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1 /*
2  * HSMCI.c
3  *
4  * Created: 9/1/2014 1:34:27 PM
5  * Author: Owais
6  */
7 #include "HSMCI.h"
8 #include "sd_mmc_protocol.h"
9 
10 //Index of current slot configured
11 static uint8_t sd_mmc_slot_sel;
13 static uint32_t hsmci_transfert_pos;
15 static uint16_t hsmci_block_size;
17 static uint16_t hsmci_nb_block;
18 
22 void hsmci_reset(void)
23 {
24  uint32_t mr = HSMCI->HSMCI_MR;
25  uint32_t dtor = HSMCI->HSMCI_DTOR;
26  uint32_t sdcr = HSMCI->HSMCI_SDCR;
27  uint32_t cstor = HSMCI->HSMCI_CSTOR;
28  uint32_t cfg = HSMCI->HSMCI_CFG;
29  HSMCI->HSMCI_CR = HSMCI_CR_SWRST;
30  HSMCI->HSMCI_MR = mr;
31  HSMCI->HSMCI_DTOR = dtor;
32  HSMCI->HSMCI_SDCR = sdcr;
33  HSMCI->HSMCI_CSTOR = cstor;
34  HSMCI->HSMCI_CFG = cfg;
35 
36  // Enable the HSMCI
37  HSMCI->HSMCI_CR = HSMCI_CR_PWSEN | HSMCI_CR_MCIEN;
38 }
39 
46 void hsmci_set_speed(uint32_t speed, uint32_t mck)
47 {
48  uint32_t clkdiv;
49  uint32_t rest;
50 
51  // Speed = MCK clock / (2 * (CLKDIV + 1))
52  if (speed > 0)
53  {
54  clkdiv = mck / (2 * speed);
55  rest = mck % (2 * speed);
56  if (rest > 0)
57  {
58  // Ensure that the card speed not be higher than expected.
59  clkdiv++;
60  }
61  if (clkdiv > 0)
62  {
63  clkdiv -= 1;
64  }
65  }
66  else
67  {
68  clkdiv = 0;
69  }
70  printf("CLKDIV is : %d\n\r",clkdiv);
71  HSMCI->HSMCI_MR &= ~HSMCI_MR_CLKDIV_Msk;
72  HSMCI->HSMCI_MR |= HSMCI_MR_CLKDIV(clkdiv);
73 }
74 
79 uint32_t hsmci_wait_busy(void)
80 {
81  uint32_t busy_wait = 1000000;
82  uint32_t sr;
83 
84  do
85  {
86  sr = HSMCI->HSMCI_SR;
87  if (busy_wait-- == 0)
88  {
89  hsmci_reset();
90  return FAIL;
91  }
92  } while (!((sr & HSMCI_SR_NOTBUSY) && ((sr & HSMCI_SR_DTIP) == 0)));
93  return OK;
94 }
95 
96 
105 uint32_t hsmci_send_cmd_execute(uint32_t cmdr, uint32_t cmd, uint32_t arg)
106 {
107  uint32_t sr;
108 
109  cmdr |= HSMCI_CMDR_CMDNB(cmd) | HSMCI_CMDR_SPCMD_STD;
110  if (cmd & SDMMC_RESP_PRESENT)
111  {
112  cmdr |= HSMCI_CMDR_MAXLAT;
113  if (cmd & SDMMC_RESP_136)
114  {
115  cmdr |= HSMCI_CMDR_RSPTYP_136_BIT;
116  }
117  else if (cmd & SDMMC_RESP_BUSY)
118  {
119  cmdr |= HSMCI_CMDR_RSPTYP_R1B;
120  }
121  else
122  {
123  cmdr |= HSMCI_CMDR_RSPTYP_48_BIT;
124  }
125  }
126  if (cmd & SDMMC_CMD_OPENDRAIN)
127  {
128  cmdr |= HSMCI_CMDR_OPDCMD_OPENDRAIN;
129  }
130 
131  // Write argument
132  HSMCI->HSMCI_ARGR = arg;
133  // Write and start command
134  HSMCI->HSMCI_CMDR = cmdr;
135 
136  // Wait end of command
137  do
138  {
139  sr = HSMCI->HSMCI_SR;
140  if (cmd & SDMMC_RESP_CRC)
141  {
142  if (sr & (HSMCI_SR_CSTOE | HSMCI_SR_RTOE | HSMCI_SR_RENDE | HSMCI_SR_RCRCE | HSMCI_SR_RDIRE | HSMCI_SR_RINDE))
143  {
144  hsmci_reset();
145  return FAIL;
146  }
147  }
148  else
149  {
150  if (sr & (HSMCI_SR_CSTOE | HSMCI_SR_RTOE | HSMCI_SR_RENDE | HSMCI_SR_RDIRE | HSMCI_SR_RINDE))
151  {
152  hsmci_reset();
153  return FAIL;
154  }
155  }
156  } while (!(sr & HSMCI_SR_CMDRDY));
157 
158  if (cmd & SDMMC_RESP_BUSY)
159  {
160  if (!hsmci_wait_busy())
161  {
162  return FAIL;
163  }
164  }
165  return OK;
166 }
167 
168 
169 //-------------------------------------------------------------------
170 //--------------------- PUBLIC FUNCTIONS ----------------------------
171 
172 uint32_t hsmci_init(void)
173 {
174  // Configure card detect pin
175  PMC->PMC_PCER0 = PMC_PCER0_PID11;
176  PIOA->PIO_PER = PIN_CDMCI;
177  PIOA->PIO_IDR = PIN_CDMCI;
178  PIOA->PIO_ODR = PIN_CDMCI;
179  PIOA->PIO_PUER = PIN_CDMCI;
180  //enable MCI's clock
181  PMC->PMC_PCER0 = PMC_PCER0_PID18;
182  //configure PIOs to be controlled by MCI
183  PIOA->PIO_PDR = PINS_MCI;
184  PIOA->PIO_IDR = PINS_MCI;
185  PIOA->PIO_ABCDSR[0] &= ~PINS_MCI; // 0 - Peripheral C
186  PIOA->PIO_ABCDSR[1] |= PINS_MCI; // 1 - Peripheral C
187  PIOA->PIO_PUER = PINS_MCI; //Pull-up enable
188  //configure MCI regs
189  //perform software reset and disable HSMCI
190  HSMCI->HSMCI_CR = HSMCI_CR_SWRST;
191  HSMCI->HSMCI_CR = HSMCI_CR_MCIDIS | HSMCI_CR_PWSDIS;
192  /* Disable all the interrupts */
193  HSMCI->HSMCI_IDR = 0xFFFFFFFF;
194  /* Set the Data Timeout Register */
195  HSMCI->HSMCI_DTOR = HSMCI_DTOR_DTOCYC_Msk | HSMCI_DTOR_DTOMUL_Msk ;
196  /* Set Completion Signal Timeout */
197  HSMCI->HSMCI_CSTOR = HSMCI_CSTOR_CSTOCYC_Msk | HSMCI_CSTOR_CSTOMUL_Msk ;
198  /* Configure MCI */
199  HSMCI->HSMCI_CFG = HSMCI_CFG_FIFOMODE | HSMCI_CFG_FERRCTRL;
200  const uint8_t CLKDIV = 0x95; //120MHz/(2x(CLKDIV+1)) = 400kHz
201  //const uint32_t MCI_CLKDIV_MASK = (uint32_t) CLKDIV; //120MHz/(2x(CLKDIV+1)) = 400kHz
202  /* Set mode register */
203  HSMCI->HSMCI_MR = CLKDIV | HSMCI_MR_RDPROOF | HSMCI_MR_WRPROOF | HSMCI_MR_PWSDIV_Msk;
204  /* Set the SDCard Register 1-bit, slot A */
205  HSMCI->HSMCI_SDCR = HSMCI_SDCR_SDCSEL_SLOTA | HSMCI_SDCR_SDCBUS_1 ;
206  /* Enable the MCI */
207  HSMCI->HSMCI_CR = HSMCI_CR_MCIEN | HSMCI_CR_PWSEN;
208  return OK;
209 }
210 
211 uint8_t hsmci_get_bus_width(uint8_t slot)
212 {
213  switch (slot) {
214  case 0:
215  //return SD_MMC_HSMCI_SLOT_0_SIZE;
216  default:
217  return 0; // Slot number wrong
218  }
219 }
220 
222 {
223  return OK;
224 }
225 
226 void hsmci_select_device(uint8_t slot, uint32_t clock, uint8_t bus_width, uint32_t high_speed)
227 {
228  uint32_t hsmci_slot = HSMCI_SDCR_SDCSEL_SLOTA;
229  uint32_t hsmci_bus_width = HSMCI_SDCR_SDCBUS_1;
230 
231  if (high_speed)
232  {
233  HSMCI->HSMCI_CFG |= HSMCI_CFG_HSMODE;
234  }
235  else
236  {
237  HSMCI->HSMCI_CFG &= ~HSMCI_CFG_HSMODE;
238  }
239 
240  hsmci_set_speed(clock, 120000000);
241 
242  switch (slot)
243  {
244  case 0:
245  hsmci_slot = HSMCI_SDCR_SDCSEL_SLOTA;
246  break;
247  //default:
248  //Assert(FAIL); // Slot number wrong
249  }
250 
251  switch (bus_width)
252  {
253  case 1:
254  hsmci_bus_width = HSMCI_SDCR_SDCBUS_1;
255  break;
256 
257  case 4:
258  hsmci_bus_width = HSMCI_SDCR_SDCBUS_4;
259  break;
260 
261  case 8:
262  hsmci_bus_width = HSMCI_SDCR_SDCBUS_8;
263  break;
264 
265  //default:
266  //Assert(FAIL); // Bus width wrong
267  }
268  HSMCI->HSMCI_SDCR = hsmci_slot | hsmci_bus_width;
269 }
270 
271 void hsmci_deselect_device(uint8_t slot)
272 {
273  //void(slot);
274  // Nothing to do
275 }
276 
278 {
279  // Configure command
280  HSMCI->HSMCI_MR &= ~(HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF | HSMCI_MR_FBYTE);
281  // Write argument
282  HSMCI->HSMCI_ARGR = 0;
283  // Write and start initialization command
284  HSMCI->HSMCI_CMDR = HSMCI_CMDR_RSPTYP_NORESP | HSMCI_CMDR_SPCMD_INIT | HSMCI_CMDR_OPDCMD_OPENDRAIN;
285  // Wait end of initialization command
286  while (!(HSMCI->HSMCI_SR & HSMCI_SR_CMDRDY));
287 }
288 
289 uint32_t hsmci_send_cmd(uint32_t cmd, uint32_t arg)
290 {
291  // Configure command
292  HSMCI->HSMCI_MR &= ~(HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF | HSMCI_MR_FBYTE);
293 #ifdef HSMCI_MR_PDCMODE
294  // Disable PDC for HSMCI
295  HSMCI->HSMCI_MR &= ~HSMCI_MR_PDCMODE;
296 #endif
297  HSMCI->HSMCI_BLKR = 0;
298  return hsmci_send_cmd_execute(0, cmd, arg);
299 }
300 
301 uint32_t hsmci_get_response(void)
302 {
303  return HSMCI->HSMCI_RSPR[0];
304 }
305 
306 void hsmci_get_response_128(uint8_t* response)
307 {
308  uint32_t response_32;
309 
310  for (uint8_t i = 0; i < 4; i++)
311  {
312  response_32 = HSMCI->HSMCI_RSPR[0];
313  *response = (response_32 >> 24) & 0xFF;
314  response++;
315  *response = (response_32 >> 16) & 0xFF;
316  response++;
317  *response = (response_32 >> 8) & 0xFF;
318  response++;
319  *response = (response_32 >> 0) & 0xFF;
320  response++;
321  }
322 }
323 
324 uint32_t hsmci_adtc_start(uint32_t cmd, uint32_t arg, uint16_t block_size, uint16_t nb_block, uint32_t access_block)
325 {
326  uint32_t cmdr;
327 
328 #ifdef HSMCI_MR_PDCMODE
329  if (access_block)
330  {
331  // Enable PDC for HSMCI
332  HSMCI->HSMCI_MR |= HSMCI_MR_PDCMODE;
333  }
334  else
335  {
336  // Disable PDC for HSMCI
337  HSMCI->HSMCI_MR &= ~HSMCI_MR_PDCMODE;
338  }
339 #endif
340 
341  // Enabling Read/Write Proof allows to stop the HSMCI Clock during
342  // read/write access if the internal FIFO is full.
343  // This will guarantee data integrity, not bandwidth.
344  HSMCI->HSMCI_MR |= HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF;
345  // Force byte transfer if needed
346  if (block_size & 0x3)
347  {
348  HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE;
349  }
350  else
351  {
352  HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE;
353  }
354 
355  if (cmd & SDMMC_CMD_WRITE)
356  {
357  cmdr = HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_WRITE;
358  }
359  else
360  {
361  cmdr = HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRDIR_READ;
362  }
363 
364  if (cmd & SDMMC_CMD_SDIO_BYTE)
365  {
366  cmdr |= HSMCI_CMDR_TRTYP_BYTE;
367  // Value 0 corresponds to a 512-byte transfer
368  HSMCI->HSMCI_BLKR = ((block_size % 512) << HSMCI_BLKR_BCNT_Pos);
369  }
370  else
371  {
372  HSMCI->HSMCI_BLKR = (block_size << HSMCI_BLKR_BLKLEN_Pos) | (nb_block << HSMCI_BLKR_BCNT_Pos);
373  if (cmd & SDMMC_CMD_SDIO_BLOCK)
374  {
375  cmdr |= HSMCI_CMDR_TRTYP_BLOCK;
376  }
377  else if (cmd & SDMMC_CMD_STREAM)
378  {
379  cmdr |= HSMCI_CMDR_TRTYP_STREAM;
380  }
381  else if (cmd & SDMMC_CMD_SINGLE_BLOCK)
382  {
383  cmdr |= HSMCI_CMDR_TRTYP_SINGLE;
384  }
385  else if (cmd & SDMMC_CMD_MULTI_BLOCK)
386  {
387  cmdr |= HSMCI_CMDR_TRTYP_MULTIPLE;
388  }
389  else
390  {
391  //Assert(FAIL); // Incorrect flags
392  printf("Incorrect flags in adtc command\n\r");
393  }
394  }
395  hsmci_transfert_pos = 0;
396  hsmci_block_size = block_size;
397  hsmci_nb_block = nb_block;
398  printf("HSMCI block size is : %d\n\r",hsmci_block_size);
399  printf("HSMCI number of blocks are : %d\n\r",nb_block);
400  return hsmci_send_cmd_execute(cmdr, cmd, arg);
401 }
402 
403 uint32_t hsmci_adtc_stop(uint32_t cmd, uint32_t arg)
404 {
405  return hsmci_send_cmd_execute(HSMCI_CMDR_TRCMD_STOP_DATA, cmd, arg);
406 }
407 
408 uint32_t hsmci_read_word(uint32_t* value)
409 {
410  uint32_t sr;
411 
412  //Assert(((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos);
413 
414  // Wait data available
415  do
416  {
417  sr = HSMCI->HSMCI_SR;
418  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | HSMCI_SR_DTOE | HSMCI_SR_DCRCE))
419  {
420  hsmci_reset();
421  return FAIL;
422  }
423  }while (!(sr & HSMCI_SR_RXRDY));
424 
425  // Read data
426  *value = HSMCI->HSMCI_RDR;
427  hsmci_transfert_pos += 4;
428  if (((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos)
429  {
430  return OK;
431  }
432 
433  // Wait end of transfer
434  // Note: no need of timeout, because it is include in HSMCI
435  do
436  {
437  sr = HSMCI->HSMCI_SR;
438  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | HSMCI_SR_DTOE | HSMCI_SR_DCRCE))
439  {
440  hsmci_reset();
441  return FAIL;
442  }
443  } while (!(sr & HSMCI_SR_XFRDONE));
444  return OK;
445 }
446 
447 uint32_t hsmci_write_word(uint32_t value)
448 {
449  uint32_t sr;
450 
451  //Assert(((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos);
452 
453  // Wait data available
454  do
455  {
456  sr = HSMCI->HSMCI_SR;
457  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | HSMCI_SR_DTOE | HSMCI_SR_DCRCE))
458  {
459  hsmci_reset();
460  return FAIL;
461  }
462  } while (!(sr & HSMCI_SR_TXRDY));
463 
464  // Write data
465  HSMCI->HSMCI_TDR = value;
466  hsmci_transfert_pos += 4;
467  if (((uint32_t)hsmci_block_size * hsmci_nb_block) > hsmci_transfert_pos)
468  {
469  return OK;
470  }
471 
472  // Wait end of transfer
473  // Note: no need of timeout, because it is include in HSMCI, see DTOE bit.
474  do
475  {
476  sr = HSMCI->HSMCI_SR;
477  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | HSMCI_SR_DTOE | HSMCI_SR_DCRCE))
478  {
479  hsmci_reset();
480  return FAIL;
481  }
482  } while (!(sr & HSMCI_SR_NOTBUSY));
483  //Assert(HSMCI->HSMCI_SR & HSMCI_SR_FIFOEMPTY);
484  return OK;
485 }
486 
487 #ifdef HSMCI_MR_PDCMODE
488 uint32_t hsmci_start_read_blocks(void *dest, uint16_t nb_block)
489 {
490  uint32_t nb_data;
491 
492  nb_data = nb_block * hsmci_block_size;
493  //Assert(nb_data <= (((uint32_t)hsmci_block_size * hsmci_nb_block) - hsmci_transfert_pos));
494  //Assert(nb_data <= (PERIPH_RCR_RXCTR_Msk >> PERIPH_RCR_RXCTR_Pos));
495 
496  // Handle unaligned memory address
497  if (((uint32_t)dest & 0x3) || (hsmci_block_size & 0x3))
498  {
499  HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE;
500  }
501  else
502  {
503  HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE;
504  }
505 
506  // Configure PDC transfer
507  HSMCI->HSMCI_RPR = (uint32_t)dest;
508  HSMCI->HSMCI_RCR = (HSMCI->HSMCI_MR & HSMCI_MR_FBYTE) ? nb_data : nb_data / 4;
509  HSMCI->HSMCI_RNCR = 0;
510  // Start transfer
511  HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTEN;
512  hsmci_transfert_pos += nb_data;
513  return OK;
514 }
515 
516 uint32_t hsmci_wait_end_of_read_blocks(void)
517 {
518  uint32_t sr;
519  // Wait end of transfer
520  // Note: no need of timeout, because it is include in HSMCI, see DTOE bit.
521  do
522  {
523  sr = HSMCI->HSMCI_SR;
524  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | HSMCI_SR_DTOE | HSMCI_SR_DCRCE))
525  {
526  HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS;
527  hsmci_reset();
528  return FAIL;
529  }
530 
531  } while (!(sr & HSMCI_SR_RXBUFF));
532 
533  if (hsmci_transfert_pos < ((uint32_t)hsmci_block_size * hsmci_nb_block))
534  {
535  return OK;
536  }
537  // It is the last transfer, then wait command completed
538  // Note: no need of timeout, because it is include in HSMCI, see DTOE bit.
539  do
540  {
541  sr = HSMCI->HSMCI_SR;
542  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | HSMCI_SR_DTOE | HSMCI_SR_DCRCE))
543  {
544  hsmci_reset();
545  return FAIL;
546  }
547  } while (!(sr & HSMCI_SR_XFRDONE));
548  return OK;
549 }
550 
551 uint32_t hsmci_start_write_blocks(const void *src, uint16_t nb_block)
552 {
553  uint32_t nb_data;
554 
555  nb_data = nb_block * hsmci_block_size;
556  //Assert(nb_data <= (((uint32_t)hsmci_block_size * hsmci_nb_block) - hsmci_transfert_pos));
557  //Assert(nb_data <= (PERIPH_TCR_TXCTR_Msk >> PERIPH_TCR_TXCTR_Pos));
558 
559  // Handle unaligned memory address
560  if (((uint32_t)src & 0x3) || (hsmci_block_size & 0x3))
561  {
562  HSMCI->HSMCI_MR |= HSMCI_MR_FBYTE;
563  }
564  else
565  {
566  HSMCI->HSMCI_MR &= ~HSMCI_MR_FBYTE;
567  }
568 
569  // Configure PDC transfer
570  HSMCI->HSMCI_TPR = (uint32_t)src;
571  HSMCI->HSMCI_TCR = (HSMCI->HSMCI_MR & HSMCI_MR_FBYTE) ? nb_data : nb_data / 4;
572  HSMCI->HSMCI_TNCR = 0;
573  // Start transfer
574  HSMCI->HSMCI_PTCR = HSMCI_PTCR_TXTEN;
575  hsmci_transfert_pos += nb_data;
576  return OK;
577 }
578 
579 uint32_t hsmci_wait_end_of_write_blocks(void)
580 {
581  uint32_t sr;
582 
583  // Wait end of transfer
584  // Note: no need of timeout, because it is include in HSMCI, see DTOE bit.
585  do
586  {
587  sr = HSMCI->HSMCI_SR;
588  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | HSMCI_SR_DTOE | HSMCI_SR_DCRCE))
589  {
590  hsmci_reset();
591  HSMCI->HSMCI_PTCR = HSMCI_PTCR_RXTDIS | HSMCI_PTCR_TXTDIS;
592  return FAIL;
593  }
594  } while (!(sr & HSMCI_SR_TXBUFE));
595 
596 
597  if (hsmci_transfert_pos < ((uint32_t)hsmci_block_size * hsmci_nb_block))
598  {
599  return OK;
600  }
601  // It is the last transfer, then wait command completed
602  // Note: no need of timeout, because it is include in HSMCI, see DTOE bit.
603  do
604  {
605  sr = HSMCI->HSMCI_SR;
606  if (sr & (HSMCI_SR_UNRE | HSMCI_SR_OVRE | HSMCI_SR_DTOE | HSMCI_SR_DCRCE))
607  {
608  hsmci_reset();
609  return FAIL;
610  }
611  } while (!(sr & HSMCI_SR_NOTBUSY));
612  //Assert(HSMCI->HSMCI_SR & HSMCI_SR_FIFOEMPTY);
613  return OK;
614 }
615 #endif // HSMCI_MR_PDCMODE
uint32_t hsmci_adtc_start(uint32_t cmd, uint32_t arg, uint16_t block_size, uint16_t nb_block, uint32_t access_block)
Send an ADTC command on the selected slot An ADTC (Addressed Data Transfer Commands) command is used ...
Definition: HSMCI.c:324
uint32_t hsmci_send_cmd_execute(uint32_t cmdr, uint32_t cmd, uint32_t arg)
Send a command.
Definition: HSMCI.c:105
uint32_t hsmci_wait_end_of_read_blocks(void)
Wait the end of transfer initiated by mci_start_read_blocks()
SD/MMC protocol definitions.
uint32_t hsmci_write_word(uint32_t value)
Write a word on the line.
Definition: HSMCI.c:447
uint32_t hsmci_is_high_speed_capable(void)
Return the high speed capability of the driver.
Definition: HSMCI.c:221
void hsmci_set_speed(uint32_t speed, uint32_t mck)
Set speed of the HSMCI clock.
Definition: HSMCI.c:46
int printf(const char *format,...)
#define SDMMC_CMD_SINGLE_BLOCK
To signal a data transfer in single block mode.
#define SDMMC_CMD_OPENDRAIN
void hsmci_select_device(uint8_t slot, uint32_t clock, uint8_t bus_width, uint32_t high_speed)
Select a slot and initialize it.
Definition: HSMCI.c:226
void hsmci_reset(void)
Reset the HSMCI interface.
Definition: HSMCI.c:22
#define PINS_MCI
Definition: HSMCI.h:19
#define SDMMC_RESP_BUSY
Card may send busy.
uint32_t hsmci_init(void)
Initializes the low level driver.
Definition: HSMCI.c:172
#define SDMMC_RESP_CRC
Expect valid crc (MCI only)
uint8_t hsmci_get_bus_width(uint8_t slot)
Return the maximum bus width of a slot.
Definition: HSMCI.c:211
uint32_t hsmci_start_write_blocks(const void *src, uint16_t nb_block)
Start a write blocks transfer on the line Note: The driver will use the DMA available to speed up the...
uint32_t hsmci_adtc_stop(uint32_t cmd, uint32_t arg)
Send a command to stop an ADTC command on the selected slot.
Definition: HSMCI.c:403
#define SDMMC_CMD_STREAM
To signal a data transfer in stream mode.
void hsmci_deselect_device(uint8_t slot)
Deselect a slot.
Definition: HSMCI.c:271
uint32_t hsmci_start_read_blocks(void *dest, uint16_t nb_block)
Start a read blocks transfer on the line Note: The driver will use the DMA available to speed up the ...
#define SDMMC_CMD_WRITE
To signal a data write operation.
#define FAIL
Definition: HSMCI.h:24
uint32_t hsmci_read_word(uint32_t *value)
Read a word on the line.
Definition: HSMCI.c:408
uint32_t hsmci_get_response(void)
Return the 32 bits response of the last command.
Definition: HSMCI.c:301
uint32_t clock
Definition: SDdrv_f.c:68
#define SDMMC_RESP_PRESENT
Have response (MCI only)
#define SDMMC_CMD_SDIO_BLOCK
To signal a SDIO tranfer in block mode.
void hsmci_get_response_128(uint8_t *response)
Return the 128 bits response of the last command.
Definition: HSMCI.c:306
uint32_t hsmci_wait_end_of_write_blocks(void)
Wait the end of transfer initiated by mci_start_write_blocks()
#define SDMMC_CMD_SDIO_BYTE
To signal a SDIO tranfer in multi byte mode.
#define SDMMC_RESP_136
136 bit response (MCI only)
#define OK
Definition: HSMCI.h:23
uint8_t high_speed
Definition: SDdrv_f.c:69
void hsmci_send_clock(void)
Send 74 clock cycles on the line of selected slot Note: It is required after card plug and before car...
Definition: HSMCI.c:277
uint32_t hsmci_wait_busy(void)
Wait the end of busy signal on data line.
Definition: HSMCI.c:79
#define PIN_CDMCI
Definition: HSMCI.h:21
#define SDMMC_CMD_MULTI_BLOCK
To signal a data transfer in multi block mode.
uint32_t hsmci_send_cmd(uint32_t cmd, uint32_t arg)
Send a command on the selected slot.
Definition: HSMCI.c:289