SAM4S-EK_FreeRTOS+FAT-SL  1.0
An example project to test the functionality of FreeRTOS+FAT-SL using SD card as data storage medium
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system_sam4s.c
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2 /* Atmel Microcontroller Software Support */
3 /* SAM Software Package License */
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29 
30 #include "sam4s.h"
31 
32 /* @cond 0 */
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38 /* @endcond */
39 
40 /* External oscillator definition, to be overriden by application */
41 #define CHIP_FREQ_XTAL_12M (12000000UL)
42 
43 #define Slow_Clock_Xtal
44 
45 #if (!defined CHIP_FREQ_XTAL)
46 # define CHIP_FREQ_XTAL CHIP_FREQ_XTAL_12M
47 #endif
48 
49 /* Clock Settings (4MHz) using Internal Fast RC */
50 uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
51 
57 void SystemInit( void )
58 {
59  /*
60  * TODO:
61  * Add code to initialize the system according to your application.
62  *
63  * For SAM4S, the internal 4MHz fast RC oscillator is the default clock
64  * selected at system reset state.
65  */
66 
67  /* Set FWS according to 120MHz clock configuration and enable Code Loop Optimization */
68  EFC0->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;
69 
70  #ifdef Slow_Clock_Xtal
71 
72  /* Switch to slow clock crystal oscillator */
73  SUPC->SUPC_CR = SUPC_CR_XTALSEL_CRYSTAL_SEL | SUPC_CR_KEY_PASSWD;
74 
75  /* Wait for switch complete */
76  while(!(SUPC->SUPC_SR & SUPC_SR_OSCSEL));
77 
78  #endif // Slow_CLock_Xtal
79 
80  /* Switch to slow clock before starting fast crystal */
81  //PMC->PMC_MCKR &= !(PMC_MCKR_CSS_Msk);
82 
83  /* Wait for master clock to be ready */
84  //while(!(PMC->PMC_SR & PMC_SR_MCKRDY));
85 
86  /* Enable Main Xtal oscillator and disable bypass. Must provide write access password for Main Oscillator Register */
87  PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST(0x40U);
88 
89  /* Wait for Xtal to stabilize */
90  while(!(PMC->PMC_SR & PMC_SR_MOSCXTS));
91 
92  /* Switch the main clock to Xtal Oscillator */
93  PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
94 
95  /* Wait for switchover */
96  while(!(PMC->PMC_SR & PMC_SR_MOSCSELS));
97 
98  /* Wait for main clock to be ready */
99  while(!(PMC->CKGR_MCFR & CKGR_MCFR_MAINFRDY));
100 
101  /* Stop PLLA */
102  PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);
103 
104  /* Configure PLLA settings */
105  PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(1) | CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_MULA(19);
106 
107  /* Wait for PLLA to be locked */
108  while(!(PMC->PMC_SR & PMC_SR_LOCKA));
109 
110  /* Set master clock prescaler */
111  PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk) | PMC_MCKR_PRES_CLK_2;
112 
113  /* Wait for master clock to be ready */
114  while(!(PMC->PMC_SR & PMC_SR_MCKRDY));
115 
116  /* Set master clock source to PLLA clock */
117  PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_PLLA_CLK;
118 
119  /* Wait for master clock to be ready */
120  while(!(PMC->PMC_SR & PMC_SR_MCKRDY));
121 
122  #ifndef KEEP_WATCHDOG_AT_INIT
123 
124  /* Disable the watchdog */
125  WDT->WDT_MR = WDT_MR_WDDIS;
126 
127  #endif
128 
129  /* Update the System Core Clock variable */
131 }
132 
137 {
138  /* Determine clock frequency according to clock register values */
139  switch ( PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk )
140  {
141  case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
142  if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL )
143  {
144  SystemCoreClock = CHIP_FREQ_XTAL_32K;
145  }
146  else
147  {
148  SystemCoreClock = CHIP_FREQ_SLCK_RC;
149  }
150  break;
151 
152  case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
153  if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
154  {
155  SystemCoreClock = CHIP_FREQ_XTAL;
156  }
157  else
158  {
159  SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
160 
161  switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
162  {
163  case CKGR_MOR_MOSCRCF_4_MHz:
164  SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
165  break;
166 
167  case CKGR_MOR_MOSCRCF_8_MHz:
168  SystemCoreClock = CHIP_FREQ_MAINCK_RC_8MHZ;
169  break;
170 
171  case CKGR_MOR_MOSCRCF_12_MHz:
172  SystemCoreClock = CHIP_FREQ_MAINCK_RC_12MHZ;
173  break;
174 
175  default:
176  break;
177  }
178  }
179  break;
180 
181  case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
182  case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */
183  if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
184  {
185  SystemCoreClock = CHIP_FREQ_XTAL;
186  }
187  else
188  {
189  SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
190 
191  switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
192  {
193  case CKGR_MOR_MOSCRCF_4_MHz:
194  SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
195  break;
196 
197  case CKGR_MOR_MOSCRCF_8_MHz:
198  SystemCoreClock = CHIP_FREQ_MAINCK_RC_8MHZ;
199  break;
200 
201  case CKGR_MOR_MOSCRCF_12_MHz:
202  SystemCoreClock = CHIP_FREQ_MAINCK_RC_12MHZ;
203  break;
204 
205  default:
206  break;
207  }
208  }
209 
210  if ( (uint32_t)(PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK )
211  {
212  SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos) + 1U);
213  SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos));
214  }
215  else
216  {
217  SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >> CKGR_PLLBR_MULB_Pos) + 1U);
218  SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >> CKGR_PLLBR_DIVB_Pos));
219  }
220  break;
221 
222  default:
223  break;
224  }
225 
226  if ( (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3 )
227  {
228  SystemCoreClock /= 3U;
229  }
230  else
231  {
232  SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
233  }
234 }
235 
241 void system_init_flash( uint32_t ul_clk )
242 {
243  /* Set FWS for embedded Flash access according to operating frequency */
244 #if !defined(ID_EFC1)
245  if ( ul_clk < CHIP_FREQ_FWS_0 )
246  {
247  EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
248  }
249  else
250  {
251  if ( ul_clk < CHIP_FREQ_FWS_1 )
252  {
253  EFC0->EEFC_FMR = EEFC_FMR_FWS(1);
254  }
255  else
256  {
257  if ( ul_clk < CHIP_FREQ_FWS_2 )
258  {
259  EFC0->EEFC_FMR = EEFC_FMR_FWS(2);
260  }
261  else
262  {
263  if ( ul_clk < CHIP_FREQ_FWS_3 )
264  {
265  EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
266  }
267  else
268  {
269  if ( ul_clk < CHIP_FREQ_FWS_4 )
270  {
271  EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
272  }
273  else
274  {
275  EFC0->EEFC_FMR = EEFC_FMR_FWS(5);
276  }
277  }
278  }
279  }
280  }
281 #else
282  if ( ul_clk < CHIP_FREQ_FWS_0 )
283  {
284  EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
285  EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
286  }
287  else
288  {
289  if ( ul_clk < CHIP_FREQ_FWS_1 )
290  {
291  EFC0->EEFC_FMR = EEFC_FMR_FWS(1);
292  EFC1->EEFC_FMR = EEFC_FMR_FWS(1);
293  }
294  else
295  {
296  if ( ul_clk < CHIP_FREQ_FWS_2 )
297  {
298  EFC0->EEFC_FMR = EEFC_FMR_FWS(2);
299  EFC1->EEFC_FMR = EEFC_FMR_FWS(2);
300  }
301  else
302  {
303  if ( ul_clk < CHIP_FREQ_FWS_3 )
304  {
305  EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
306  EFC1->EEFC_FMR = EEFC_FMR_FWS(3);
307  }
308  else
309  {
310  if ( ul_clk < CHIP_FREQ_FWS_4 )
311  {
312  EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
313  EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
314  }
315  else
316  {
317  EFC0->EEFC_FMR = EEFC_FMR_FWS(5);
318  EFC1->EEFC_FMR = EEFC_FMR_FWS(5);
319  }
320  }
321  }
322  }
323  }
324 #endif
325 }
326 
327 /* @cond 0 */
329 #ifdef __cplusplus
330 }
331 #endif
332 
333 /* @endcond */
uint32_t SystemCoreClock
Definition: system_sam4s.c:50
void SystemInit(void)
Setup the microcontroller system.
Definition: system_sam4s.c:57
void SystemCoreClockUpdate(void)
Get Core Clock Frequency.
Definition: system_sam4s.c:136
void system_init_flash(uint32_t ul_clk)
Initialize flash wait state according to operating frequency.
Definition: system_sam4s.c:241
#define CHIP_FREQ_XTAL
Definition: system_sam4s.c:46