SAM4S-EK_FreeRTOS+FAT-SL  1.0
An example project to test the functionality of FreeRTOS+FAT-SL using SD card as data storage medium
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sd_mmc_protocol.h
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1 
44 #ifndef SD_MMC_PROTOCOL_H_INCLUDED
45 #define SD_MMC_PROTOCOL_H_INCLUDED
46 
47 #include "sd_mmc_protocol.h"
48 
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 
59 // SD/MMC/SDIO default clock frequency for initialization (400KHz)
60 #define SDMMC_CLOCK_INIT 400000
61 
62 
108 typedef uint32_t sdmmc_cmd_def_t;
110 
113 #define SDMMC_CMD_GET_INDEX(cmd) (cmd & 0x3F)
114 #define SDMMC_RESP_PRESENT (1lu << 8)
116 #define SDMMC_RESP_8 (1lu << 9)
118 #define SDMMC_RESP_32 (1lu << 10)
120 #define SDMMC_RESP_136 (1lu << 11)
122 #define SDMMC_RESP_CRC (1lu << 12)
124 #define SDMMC_RESP_BUSY (1lu << 13)
126 // Open drain for a braodcast command (bc)
127 // or to enter in inactive state (MCI only)
128 #define SDMMC_CMD_OPENDRAIN (1lu << 14)
129 #define SDMMC_CMD_WRITE (1lu << 15)
131 #define SDMMC_CMD_SDIO_BYTE (1lu << 16)
133 #define SDMMC_CMD_SDIO_BLOCK (1lu << 17)
135 #define SDMMC_CMD_STREAM (1lu << 18)
137 #define SDMMC_CMD_SINGLE_BLOCK (1lu << 19)
139 #define SDMMC_CMD_MULTI_BLOCK (1lu << 20)
141 
145 #define SDMMC_CMD_NO_RESP (0)
146 #define SDMMC_CMD_R1 (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC)
147 #define SDMMC_CMD_R1B (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC | SDMMC_RESP_BUSY)
148 #define SDMMC_CMD_R2 (SDMMC_RESP_PRESENT | SDMMC_RESP_8 | SDMMC_RESP_136 | SDMMC_RESP_CRC)
149 #define SDMMC_CMD_R3 (SDMMC_RESP_PRESENT | SDMMC_RESP_32)
150 #define SDMMC_CMD_R4 (SDMMC_RESP_PRESENT | SDMMC_RESP_32)
151 #define SDMMC_CMD_R5 (SDMMC_RESP_PRESENT | SDMMC_RESP_8 | SDMMC_RESP_CRC)
152 #define SDMMC_CMD_R6 (SDMMC_RESP_PRESENT | SDMMC_RESP_CRC)
153 #define SDMMC_CMD_R7 (SDMMC_RESP_PRESENT | SDMMC_RESP_32 | SDMMC_RESP_CRC)
154 
162 
163 /*
164  * --- Basic commands and read-stream command (class 0 and class 1) ---
165  */
166 
168 #define SDMMC_SPI_CMD0_GO_IDLE_STATE (0 | SDMMC_CMD_R1)
169 #define SDMMC_MCI_CMD0_GO_IDLE_STATE (0 | SDMMC_CMD_NO_RESP | SDMMC_CMD_OPENDRAIN)
170 
171 #define MMC_SPI_CMD1_SEND_OP_COND (1 | SDMMC_CMD_R1)
172 #define MMC_MCI_CMD1_SEND_OP_COND (1 | SDMMC_CMD_R3 | SDMMC_CMD_OPENDRAIN)
173 
174 #define SDMMC_CMD2_ALL_SEND_CID (2 | SDMMC_CMD_R2 | SDMMC_CMD_OPENDRAIN)
175 
176 #define SD_CMD3_SEND_RELATIVE_ADDR (3 | SDMMC_CMD_R6 | SDMMC_CMD_OPENDRAIN)
177 
178 #define MMC_CMD3_SET_RELATIVE_ADDR (3 | SDMMC_CMD_R1)
179 
180 #define SDMMC_CMD4_SET_DSR (4 | SDMMC_CMD_NO_RESP)
181 
182 #define MMC_CMD5_SLEEP_AWAKE (5 | SDMMC_CMD_R1B)
183 
188 #define SDMMC_CMD7_SELECT_CARD_CMD (7 | SDMMC_CMD_R1B)
189 #define SDMMC_CMD7_DESELECT_CARD_CMD (7 | SDMMC_CMD_R1)
190 
191 #define MMC_CMD8_SEND_EXT_CSD (8 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
192 
193 #define SD_CMD8_SEND_IF_COND (8 | SDMMC_CMD_R7 | SDMMC_CMD_OPENDRAIN)
194 
195 #define SDMMC_SPI_CMD9_SEND_CSD (9 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
196 
197 #define SDMMC_MCI_CMD9_SEND_CSD (9 | SDMMC_CMD_R2)
198 
199 #define SDMMC_CMD10_SEND_CID (10 | SDMMC_CMD_R2)
200 
204 #define MMC_CMD11_READ_DAT_UNTIL_STOP (11 | SDMMC_CMD_R1)
205 /* SD Cmd11 MCI (ac, R1): Voltage switching */
206 #define SD_CMD11_READ_DAT_UNTIL_STOP (11 | SDMMC_CMD_R1)
207 
208 #define SDMMC_CMD12_STOP_TRANSMISSION (12 | SDMMC_CMD_R1B)
209 
210 #define SDMMC_SPI_CMD13_SEND_STATUS (13 | SDMMC_CMD_R2)
211 
212 #define SDMMC_MCI_CMD13_SEND_STATUS (13 | SDMMC_CMD_R1)
213 
214 #define MMC_CMD14_BUSTEST_R (14 | SDMMC_CMD_R1)
215 
216 // Note: It is a ac cmd, but it must be send like bc cmd to open drain
217 #define SDMMC_CMD15_GO_INACTIVE_STATE (15 | SDMMC_CMD_NO_RESP | SDMMC_CMD_OPENDRAIN)
218 
219 #define MMC_CMD19_BUSTEST_W (19 | SDMMC_CMD_R1)
220 
221 #define SDMMC_SPI_CMD58_READ_OCR (58 | SDMMC_CMD_R3)
222 
223 #define SDMMC_SPI_CMD59_CRC_ON_OFF (59 | SDMMC_CMD_R1)
224 
225 /*
226  * --- Block-oriented read commands (class 2) ---
227  */
229 #define SDMMC_CMD16_SET_BLOCKLEN (16 | SDMMC_CMD_R1)
230 
231 #define SDMMC_CMD17_READ_SINGLE_BLOCK (17 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
232 
233 #define SDMMC_CMD18_READ_MULTIPLE_BLOCK (18 | SDMMC_CMD_R1 | SDMMC_CMD_MULTI_BLOCK)
234 
235 /*
236  * --- Sequential write commands (class 3) ---
237  */
238 
243 #define MMC_CMD20_WRITE_DAT_UNTIL_STOP (20 | SDMMC_CMD_R1)
244 
245 /*
246  * --- Block-oriented write commands (class 4) ---
247  */
249 #define MMC_CMD23_SET_BLOCK_COUNT (23 | SDMMC_CMD_R1)
250 
251 #define SDMMC_CMD24_WRITE_BLOCK (24 | SDMMC_CMD_R1 | SDMMC_CMD_WRITE | SDMMC_CMD_SINGLE_BLOCK)
252 
253 #define SDMMC_CMD25_WRITE_MULTIPLE_BLOCK (25 | SDMMC_CMD_R1 | SDMMC_CMD_WRITE | SDMMC_CMD_MULTI_BLOCK)
254 
255 #define MMC_CMD26_PROGRAM_CID (26 | SDMMC_CMD_R1)
256 
257 #define SDMMC_CMD27_PROGRAM_CSD (27 | SDMMC_CMD_R1)
258 
259 /*
260  * --- Erase commands (class 5) ---
261  */
263 #define SD_CMD32_ERASE_WR_BLK_START (32 | SDMMC_CMD_R1)
264 
265 #define SD_CMD33_ERASE_WR_BLK_END (33 | SDMMC_CMD_R1)
266 
267 #define MMC_CMD35_ERASE_GROUP_START (35 | SDMMC_CMD_R1)
268 
269 #define MMC_CMD36_ERASE_GROUP_END (36 | SDMMC_CMD_R1)
270 
271 #define SDMMC_CMD38_ERASE (38 | SDMMC_CMD_R1B)
272 
273 /*
274  * --- Block Oriented Write Protection Commands (class 6) ---
275  */
277 #define SDMMC_CMD28_SET_WRITE_PROT (28 | SDMMC_CMD_R1B)
278 
279 #define SDMMC_CMD29_CLR_WRITE_PROT (29 | SDMMC_CMD_R1B)
280 
281 #define SDMMC_CMD30_SEND_WRITE_PROT (30 | SDMMC_CMD_R1)
282 
283 /*
284  * --- Lock Card (class 7) ---
285  */
287 #define SDMMC_CMD42_LOCK_UNLOCK (42 | SDMMC_CMD_R1)
288 
289 /*
290  * --- Application-specific commands (class 8) ---
291  */
296 #define SDMMC_CMD55_APP_CMD (55 | SDMMC_CMD_R1)
297 
301 #define SDMMC_CMD56_GEN_CMD (56 | SDMMC_CMD_R1)
302 
307 #define MMC_CMD6_SWITCH (6 | SDMMC_CMD_R1B)
308 
312 #define SD_CMD6_SWITCH_FUNC (6 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
313 
314 #define SD_ACMD6_SET_BUS_WIDTH (6 | SDMMC_CMD_R1)
315 
316 #define SD_ACMD13_SD_STATUS (13 | SDMMC_CMD_R1)
317 
321 #define SD_ACMD22_SEND_NUM_WR_BLOCKS (22 | SDMMC_CMD_R1)
322 
326 #define SD_ACMD23_SET_WR_BLK_ERASE_COUNT (23 | SDMMC_CMD_R1)
327 
332 #define SD_MCI_ACMD41_SD_SEND_OP_COND (41 | SDMMC_CMD_R3 | SDMMC_CMD_OPENDRAIN)
333 
337 #define SD_SPI_ACMD41_SD_SEND_OP_COND (41 | SDMMC_CMD_R1)
338 
342 #define SD_ACMD42_SET_CLR_CARD_DETECT (42 | SDMMC_CMD_R1)
343 
344 #define SD_ACMD51_SEND_SCR (51 | SDMMC_CMD_R1 | SDMMC_CMD_SINGLE_BLOCK)
345 
346 /*
347  * --- I/O mode commands (class 9) ---
348  */
350 #define MMC_CMD39_FAST_IO (39 | SDMMC_CMD_R4)
351 
352 #define MMC_CMD40_GO_IRQ_STATE (40 | SDMMC_CMD_R5 | SDMMC_CMD_OPENDRAIN)
353 
354 #define SDIO_CMD5_SEND_OP_COND (5 | SDMMC_CMD_R4 | SDMMC_CMD_OPENDRAIN)
355 
356 #define SDIO_CMD52_IO_RW_DIRECT (52 | SDMMC_CMD_R5)
357 
358 #define SDIO_CMD53_IO_R_BYTE_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BYTE)
359 #define SDIO_CMD53_IO_W_BYTE_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BYTE | SDMMC_CMD_WRITE)
360 #define SDIO_CMD53_IO_R_BLOCK_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BLOCK)
361 #define SDIO_CMD53_IO_W_BLOCK_EXTENDED (53 | SDMMC_CMD_R5 | SDMMC_CMD_SDIO_BLOCK | SDMMC_CMD_WRITE)
362 
365 
368 
373 #define MMC_CMD6_ACCESS_COMMAND_SET (0lu << 24)
374 #define MMC_CMD6_ACCESS_SET_BITS (1lu << 24)
375 #define MMC_CMD6_ACCESS_CLEAR_BITS (2lu << 24)
376 #define MMC_CMD6_ACCESS_WRITE_BYTE (3lu << 24)
377 #define MMC_CMD6_INDEX_CMD_SET (EXT_CSD_CMD_SET_INDEX << 16)
379 #define MMC_CMD6_INDEX_CMD_SET_REV (EXT_CSD_CMD_SET_REV_INDEX << 16)
380 #define MMC_CMD6_INDEX_POWER_CLASS (EXT_CSD_POWER_CLASS_INDEX << 16)
381 #define MMC_CMD6_INDEX_HS_TIMING (EXT_CSD_HS_TIMING_INDEX << 16)
382 #define MMC_CMD6_INDEX_BUS_WIDTH (EXT_CSD_BUS_WIDTH_INDEX << 16)
383 #define MMC_CMD6_INDEX_ERASED_MEM_CONT (EXT_CSD_ERASED_MEM_CONT_INDEX << 16)
384 #define MMC_CMD6_INDEX_BOOT_CONFIG (EXT_CSD_BOOT_CONFIG_INDEX << 16)
385 #define MMC_CMD6_INDEX_BOOT_BUS_WIDTH (EXT_CSD_BOOT_BUS_WIDTH_INDEX << 16)
386 #define MMC_CMD6_INDEX_ERASE_GROUP_DEF (EXT_CSD_ERASE_GROUP_DEF_INDEX << 16)
387 #define MMC_CMD6_VALUE_BUS_WIDTH_1BIT (0x0lu << 8)
389 #define MMC_CMD6_VALUE_BUS_WIDTH_4BIT (0x1lu << 8)
390 #define MMC_CMD6_VALUE_BUS_WIDTH_8BIT (0x2lu << 8)
391 #define MMC_CMD6_VALUE_HS_TIMING_ENABLE (0x1lu << 8)
392 #define MMC_CMD6_VALUE_HS_TIMING_DISABLE (0x0lu << 8)
393 
400 #define SD_CMD6_GRP1_HIGH_SPEED (0x1lu << 0)
401 #define SD_CMD6_GRP1_DEFAULT (0x0lu << 0)
402 #define SD_CMD6_GRP2_NO_INFLUENCE (0xFlu << 4)
404 #define SD_CMD6_GRP2_DEFAULT (0x0lu << 4)
405 #define SD_CMD6_GRP3_NO_INFLUENCE (0xFlu << 8)
407 #define SD_CMD6_GRP3_DEFAULT (0x0lu << 8)
408 #define SD_CMD6_GRP4_NO_INFLUENCE (0xFlu << 12)
410 #define SD_CMD6_GRP4_DEFAULT (0x0lu << 12)
411 #define SD_CMD6_GRP5_NO_INFLUENCE (0xFlu << 16)
413 #define SD_CMD6_GRP5_DEFAULT (0x0lu << 16)
414 #define SD_CMD6_GRP6_NO_INFLUENCE (0xFlu << 20)
416 #define SD_CMD6_GRP6_DEFAULT (0x0lu << 20)
417 #define SD_CMD6_MODE_CHECK (0lu << 31)
420 #define SD_CMD6_MODE_SWITCH (1lu << 31)
421 
425 #define SD_CMD8_PATTERN 0xAA
426 #define SD_CMD8_MASK_PATTERN 0xFF
427 #define SD_CMD8_HIGH_VOLTAGE 0x100
428 #define SD_CMD8_MASK_VOLTAGE 0xF00
429 
433 #define SD_ACMD41_HCS (1lu << 30)
434 
437 
440 
443 #define SDIO_R5_COM_CRC_ERROR (1lu << 15)
444 #define SDIO_R5_ILLEGAL_COMMAND (1lu << 14)
445 #define SDIO_R5_STATE (3lu << 12)
446 #define SDIO_R5_STATE_DIS (0lu << 12)
447 #define SDIO_R5_STATE_CMD (1lu << 12)
448 #define SDIO_R5_STATE_TRN (2lu << 12)
449 #define SDIO_R5_STATE_RFU (3lu << 12)
450 #define SDIO_R5_ERROR (1lu << 11)
451 #define SDIO_R5_FUNC_NUM (1lu << 9)
452 #define SDIO_R5_OUT_OF_RANGE (1lu << 8)
453 #define SDIO_R5_STATUS_ERR (SDIO_R5_ERROR | SDIO_R5_FUNC_NUM \
454  | SDIO_R5_OUT_OF_RANGE)
455 
457 
460 #define SDIO_R6_COM_CRC_ERROR (1lu << 15)
461 
462 #define SDIO_R6_ILLEGAL_COMMAND (1lu << 14)
463 
464 #define SDIO_R6_ERROR (1lu << 13)
465 
466 #define SDIO_STATUS_R6 (SDIO_R6_COM_CRC_ERROR \
467  | SDIO_R6_ILLEGAL_COMMAND | SDIO_R6_ERROR)
468 
473 #define SDIO_CMD52_WR_DATA 0
474 #define SDIO_CMD52_STUFF0 8
476 #define SDIO_CMD52_REG_ADRR 9
478 #define SDIO_CMD52_STUFF1 26
480 #define SDIO_CMD52_RAW_FLAG 27
482 #define SDIO_CMD52_FUNCTION_NUM 28
484 #define SDIO_CMD52_RW_FLAG 31
486 # define SDIO_CMD52_READ_FLAG 0
487 # define SDIO_CMD52_WRITE_FLAG 1
488 
492 
498 #define SDIO_CMD53_COUNT 0
499 #define SDIO_CMD53_REG_ADDR 9
501 #define SDIO_CMD53_OP_CODE 26
503 #define SDIO_CMD53_BLOCK_MODE 27
505 #define SDIO_CMD53_FUNCTION_NUM 28
507 #define SDIO_CMD53_RW_FLAG 31
509 # define SDIO_CMD53_READ_FLAG 0
510 # define SDIO_CMD53_WRITE_FLAG 1
511 
515 #define SDIO_CIA 0
516 #define SDIO_FN0 0
517 #define SDIO_FN1 1
518 #define SDIO_FN2 2
519 #define SDIO_FN3 3
520 #define SDIO_FN4 4
521 #define SDIO_FN5 5
522 #define SDIO_FN6 6
523 #define SDIO_FN7 7
524 
526 #define SDIO_CCCR_SDIO_REV 0x00
529 #define SDIO_CCCR_REV_1_00 (0x0lu << 0)
530 #define SDIO_CCCR_REV_1_10 (0x1lu << 0)
531 #define SDIO_CCCR_REV_2_00 (0x2lu << 0)
532 #define SDIO_CCCR_REV_3_00 (0x3lu << 0)
533 #define SDIO_SDIO_REV_1_00 (0x0lu << 4)
534 #define SDIO_SDIO_REV_1_10 (0x1lu << 4)
535 #define SDIO_SDIO_REV_1_20 (0x2lu << 4)
536 #define SDIO_SDIO_REV_2_00 (0x3lu << 4)
537 #define SDIO_SDIO_REV_3_00 (0x4lu << 4)
538 #define SDIO_CCCR_SD_REV 0x01
539 #define SDIO_SD_REV_1_01 (0x0lu << 0)
540 #define SDIO_SD_REV_1_10 (0x1lu << 0)
541 #define SDIO_SD_REV_2_00 (0x2lu << 0)
542 #define SDIO_SD_REV_3_00 (0x3lu << 0)
543 #define SDIO_CCCR_IOE 0x02
544 #define SDIO_IOE_FN1 (0x1lu << 1)
545 #define SDIO_IOE_FN2 (0x1lu << 2)
546 #define SDIO_IOE_FN3 (0x1lu << 3)
547 #define SDIO_IOE_FN4 (0x1lu << 4)
548 #define SDIO_IOE_FN5 (0x1lu << 5)
549 #define SDIO_IOE_FN6 (0x1lu << 6)
550 #define SDIO_IOE_FN7 (0x1lu << 7)
551 #define SDIO_CCCR_IOR 0x03
552 #define SDIO_IOR_FN1 (0x1lu << 1)
553 #define SDIO_IOR_FN2 (0x1lu << 2)
554 #define SDIO_IOR_FN3 (0x1lu << 3)
555 #define SDIO_IOR_FN4 (0x1lu << 4)
556 #define SDIO_IOR_FN5 (0x1lu << 5)
557 #define SDIO_IOR_FN6 (0x1lu << 6)
558 #define SDIO_IOR_FN7 (0x1lu << 7)
559 #define SDIO_CCCR_IEN 0x04
560 #define SDIO_IENM (0x1lu << 0)
561 #define SDIO_IEN_FN1 (0x1lu << 1)
562 #define SDIO_IEN_FN2 (0x1lu << 2)
563 #define SDIO_IEN_FN3 (0x1lu << 3)
564 #define SDIO_IEN_FN4 (0x1lu << 4)
565 #define SDIO_IEN_FN5 (0x1lu << 5)
566 #define SDIO_IEN_FN6 (0x1lu << 6)
567 #define SDIO_IEN_FN7 (0x1lu << 7)
568 #define SDIO_CCCR_INT 0x05
569 #define SDIO_INT_FN1 (0x1lu << 1)
570 #define SDIO_INT_FN2 (0x1lu << 2)
571 #define SDIO_INT_FN3 (0x1lu << 3)
572 #define SDIO_INT_FN4 (0x1lu << 4)
573 #define SDIO_INT_FN5 (0x1lu << 5)
574 #define SDIO_INT_FN6 (0x1lu << 6)
575 #define SDIO_INT_FN7 (0x1lu << 7)
576 #define SDIO_CCCR_IOA 0x06
577 #define SDIO_AS_FN1 (0x1lu << 0)
578 #define SDIO_AS_FN2 (0x2lu << 0)
579 #define SDIO_AS_FN3 (0x3lu << 0)
580 #define SDIO_AS_FN4 (0x4lu << 0)
581 #define SDIO_AS_FN5 (0x5lu << 0)
582 #define SDIO_AS_FN6 (0x6lu << 0)
583 #define SDIO_AS_FN7 (0x7lu << 0)
584 #define SDIO_RES (0x1lu << 3)
585 #define SDIO_CCCR_BUS_CTRL 0x07
586 #define SDIO_BUSWIDTH_1B (0x0lu << 0)
587 #define SDIO_BUSWIDTH_4B (0x2lu << 0)
589 #define SDIO_BUS_ECSI (0x1lu << 5)
590 
591 #define SDIO_BUS_SCSI (0x1lu << 6)
592 
593 #define SDIO_BUS_CD_DISABLE (0x1lu << 7)
594 #define SDIO_CCCR_CAP 0x08
596 #define SDIO_CAP_SDC (0x1lu << 0)
597 
598 #define SDIO_CAP_SMB (0x1lu << 1)
599 
600 #define SDIO_CAP_SRW (0x1lu << 2)
601 
602 #define SDIO_CAP_SBS (0x1lu << 3)
603 
604 #define SDIO_CAP_S4MI (0x1lu << 4)
605 
606 #define SDIO_CAP_E4MI (0x1lu << 5)
607 
608 #define SDIO_CAP_LSC (0x1lu << 6)
609 
610 #define SDIO_CAP_4BLS (0x1lu << 7)
611 
612 #define SDIO_CCCR_CIS_PTR 0x09
613 
614 #define SDIO_CCCR_BUS_SUSPEND 0x0C
615 
616 #define SDIO_BS (0x1lu << 0)
617 
618 #define SDIO_BR (0x1lu << 1)
619 #define SDIO_CCCR_FUN_SEL 0x0D
620 #define SDIO_DF (0x1lu << 7)
621 #define SDIO_FS_CIA (0x0lu << 0)
622 #define SDIO_FS_FN1 (0x1lu << 0)
623 #define SDIO_FS_FN2 (0x2lu << 0)
624 #define SDIO_FS_FN3 (0x3lu << 0)
625 #define SDIO_FS_FN4 (0x4lu << 0)
626 #define SDIO_FS_FN5 (0x5lu << 0)
627 #define SDIO_FS_FN6 (0x6lu << 0)
628 #define SDIO_FS_FN7 (0x7lu << 0)
629 #define SDIO_FS_MEM (0x8lu << 0)
630 #define SDIO_CCCR_EXEC 0x0E
631 #define SDIO_EXM (0x1lu << 0)
632 #define SDIO_EX_FN1 (0x1lu << 1)
633 #define SDIO_EX_FN2 (0x1lu << 2)
634 #define SDIO_EX_FN3 (0x1lu << 3)
635 #define SDIO_EX_FN4 (0x1lu << 4)
636 #define SDIO_EX_FN5 (0x1lu << 5)
637 #define SDIO_EX_FN6 (0x1lu << 6)
638 #define SDIO_EX_FN7 (0x1lu << 7)
639 #define SDIO_CCCR_READY 0x0F
640 #define SDIO_RFM (0x1lu << 0)
641 #define SDIO_RF_FN1 (0x1lu << 1)
642 #define SDIO_RF_FN2 (0x1lu << 2)
643 #define SDIO_RF_FN3 (0x1lu << 3)
644 #define SDIO_RF_FN4 (0x1lu << 4)
645 #define SDIO_RF_FN5 (0x1lu << 5)
646 #define SDIO_RF_FN6 (0x1lu << 6)
647 #define SDIO_RF_FN7 (0x1lu << 7)
648 #define SDIO_CCCR_FN0_BLKSIZ 0x10
649 #define SDIO_CCCR_POWER 0x12
650 #define SDIO_POWER_SMPC (0x1lu << 0)
651 #define SDIO_POWER_EMPC (0x1lu << 1)
652 #define SDIO_CCCR_HS 0x13
653 #define SDIO_SHS (0x1lu << 0)
654 #define SDIO_EHS (0x1lu << 1)
655 
657 
660 #define SDIO_CISTPL_NULL 0x00
661 
662 #define SDIO_CISTPL_DEVICE 0x01
663 
664 #define SDIO_CISTPL_CHECKSUM 0x10
665 
666 #define SDIO_CISTPL_VERS_1 0x15
667 
668 #define SDIO_CISTPL_ALTSTR 0x16
669 
670 #define SDIO_CISTPL_MANFID 0x20
671 
672 #define SDIO_CISTPL_FUNCID 0x21
673 
674 #define SDIO_CISTPL_FUNCE 0x22
675 
676 #define SDIO_CISTPL_SDIO_STD 0x91
677 
678 #define SDIO_CISTPL_SDIO_EXT 0x92
679 
680 #define SDIO_CISTPL_END 0xFF
681 
684 
687 
692 static inline uint32_t SDMMC_UNSTUFF_BITS(uint8_t *reg, uint16_t reg_size,
693  uint16_t pos, uint8_t size)
694 {
695  uint32_t value;
696  value = reg[((reg_size - pos + 7) / 8) - 1] >> (pos % 8);
697  if (((pos % 8) + size) > 8) {
698  value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 2] << (8 - (pos % 8));
699  }
700  if (((pos % 8) + size) > 16) {
701  value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
702  }
703  if (((pos % 8) + size) > 16) {
704  value |= (uint32_t)reg[((reg_size - pos + 7) / 8) - 3] << (16 - (pos % 8));
705  }
706  value &= ((uint32_t)1 << size) - 1;
707  return value;
708 }
709 
712 #define CSD_REG_BIT_SIZE 128
713 #define CSD_REG_BSIZE (CSD_REG_BIT_SIZE / 8)
714 #define CSD_STRUCTURE(csd, pos, size) \
715  SDMMC_UNSTUFF_BITS(csd, CSD_REG_BIT_SIZE, pos, size)
716 #define CSD_STRUCTURE_VERSION(csd) CSD_STRUCTURE(csd, 126, 2)
717 #define SD_CSD_VER_1_0 0
718 #define SD_CSD_VER_2_0 1
719 #define MMC_CSD_VER_1_0 0
720 #define MMC_CSD_VER_1_1 1
721 #define MMC_CSD_VER_1_2 2
722 #define CSD_TRAN_SPEED(csd) CSD_STRUCTURE(csd, 96, 8)
723 #define SD_CSD_1_0_C_SIZE(csd) CSD_STRUCTURE(csd, 62, 12)
724 #define SD_CSD_1_0_C_SIZE_MULT(csd) CSD_STRUCTURE(csd, 47, 3)
725 #define SD_CSD_1_0_READ_BL_LEN(csd) CSD_STRUCTURE(csd, 80, 4)
726 #define SD_CSD_2_0_C_SIZE(csd) CSD_STRUCTURE(csd, 48, 22)
727 #define MMC_CSD_C_SIZE(csd) CSD_STRUCTURE(csd, 62, 12)
728 #define MMC_CSD_C_SIZE_MULT(csd) CSD_STRUCTURE(csd, 47, 3)
729 #define MMC_CSD_READ_BL_LEN(csd) CSD_STRUCTURE(csd, 80, 4)
730 #define MMC_CSD_SPEC_VERS(csd) CSD_STRUCTURE(csd, 122, 4)
731 
735 #define OCR_REG_BSIZE (32 / 8)
736 #define OCR_VDD_170_195 (1lu << 7)
737 #define OCR_VDD_20_21 (1lu << 8)
738 #define OCR_VDD_21_22 (1lu << 9)
739 #define OCR_VDD_22_23 (1lu << 10)
740 #define OCR_VDD_23_24 (1lu << 11)
741 #define OCR_VDD_24_25 (1lu << 12)
742 #define OCR_VDD_25_26 (1lu << 13)
743 #define OCR_VDD_26_27 (1lu << 14)
744 #define OCR_VDD_27_28 (1lu << 15)
745 #define OCR_VDD_28_29 (1lu << 16)
746 #define OCR_VDD_29_30 (1lu << 17)
747 #define OCR_VDD_30_31 (1lu << 18)
748 #define OCR_VDD_31_32 (1lu << 19)
749 #define OCR_VDD_32_33 (1lu << 20)
750 #define OCR_VDD_33_34 (1lu << 21)
751 #define OCR_VDD_34_35 (1lu << 22)
752 #define OCR_VDD_35_36 (1lu << 23)
753 #define OCR_SDIO_S18R (1lu << 24)
754 #define OCR_SDIO_MP (1lu << 27)
755 #define OCR_SDIO_NF (7lu << 28)
756 #define OCR_ACCESS_MODE_MASK (3lu << 29)
757 #define OCR_ACCESS_MODE_BYTE (0lu << 29)
758 #define OCR_ACCESS_MODE_SECTOR (2lu << 29)
759 #define OCR_CCS (1lu << 30)
760 #define OCR_POWER_UP_BUSY (1lu << 31)
761 
763 #define SD_SCR_REG_BIT_SIZE 64
766 #define SD_SCR_REG_BSIZE (SD_SCR_REG_BIT_SIZE / 8)
767 #define SD_SCR_STRUCTURE(scr, pos, size) \
768  SDMMC_UNSTUFF_BITS(scr, SD_SCR_REG_BIT_SIZE, pos, size)
769 #define SD_SCR_SCR_STRUCTURE(scr) SD_SCR_STRUCTURE(scr, 60, 4)
770 #define SD_SCR_SCR_STRUCTURE_1_0 0
771 #define SD_SCR_SD_SPEC(scr) SD_SCR_STRUCTURE(scr, 56, 4)
772 #define SD_SCR_SD_SPEC_1_0_01 0
773 #define SD_SCR_SD_SPEC_1_10 1
774 #define SD_SCR_SD_SPEC_2_00 2
775 #define SD_SCR_DATA_STATUS_AFTER_ERASE(scr) SD_SCR_STRUCTURE(scr, 55, 1)
776 #define SD_SCR_SD_SECURITY(scr) SD_SCR_STRUCTURE(scr, 52, 3)
777 #define SD_SCR_SD_SECURITY_NO 0
778 #define SD_SCR_SD_SECURITY_NOTUSED 1
779 #define SD_SCR_SD_SECURITY_1_01 2
780 #define SD_SCR_SD_SECURITY_2_00 3
781 #define SD_SCR_SD_SECURITY_3_00 4
782 #define SD_SCR_SD_BUS_WIDTHS(scr) SD_SCR_STRUCTURE(scr, 48, 4)
783 #define SD_SCR_SD_BUS_WIDTH_1BITS (1lu << 0)
784 #define SD_SCR_SD_BUS_WIDTH_4BITS (1lu << 2)
785 #define SD_SCR_SD_SPEC3(scr) SD_SCR_STRUCTURE(scr, 47, 1)
786 #define SD_SCR_SD_SPEC_3_00 1
787 #define SD_SCR_SD_EX_SECURITY(scr) SD_SCR_STRUCTURE(scr, 43, 4)
788 #define SD_SCR_SD_CMD_SUPPORT(scr) SD_SCR_STRUCTURE(scr, 32, 2)
789 
793 #define SD_SW_STATUS_BIT_SIZE 512
794 #define SD_SW_STATUS_BSIZE (SD_SW_STATUS_BIT_SIZE / 8)
795 #define SD_SW_STATUS_STRUCTURE(sd_sw_status, pos, size) \
796  SDMMC_UNSTUFF_BITS(sd_sw_status, SD_SW_STATUS_BIT_SIZE, pos, size)
797 #define SD_SW_STATUS_MAX_CURRENT_CONSUMPTION(status) \
798  SD_SW_STATUS_STRUCTURE(status, 496, 16)
799 #define SD_SW_STATUS_FUN_GRP6_INFO(status) \
800  SD_SW_STATUS_STRUCTURE(status, 480, 16)
801 #define SD_SW_STATUS_FUN_GRP5_INFO(status) \
802  SD_SW_STATUS_STRUCTURE(status, 464, 16)
803 #define SD_SW_STATUS_FUN_GRP4_INFO(status) \
804  SD_SW_STATUS_STRUCTURE(status, 448, 16)
805 #define SD_SW_STATUS_FUN_GRP3_INFO(status) \
806  SD_SW_STATUS_STRUCTURE(status, 432, 16)
807 #define SD_SW_STATUS_FUN_GRP2_INFO(status) \
808  SD_SW_STATUS_STRUCTURE(status, 416, 16)
809 #define SD_SW_STATUS_FUN_GRP1_INFO(status) \
810  SD_SW_STATUS_STRUCTURE(status, 400, 16)
811 #define SD_SW_STATUS_FUN_GRP6_RC(status) \
812  SD_SW_STATUS_STRUCTURE(status, 396, 4)
813 #define SD_SW_STATUS_FUN_GRP5_RC(status) \
814  SD_SW_STATUS_STRUCTURE(status, 392, 4)
815 #define SD_SW_STATUS_FUN_GRP4_RC(status) \
816  SD_SW_STATUS_STRUCTURE(status, 388, 4)
817 #define SD_SW_STATUS_FUN_GRP3_RC(status) \
818  SD_SW_STATUS_STRUCTURE(status, 384, 4)
819 #define SD_SW_STATUS_FUN_GRP2_RC(status) \
820  SD_SW_STATUS_STRUCTURE(status, 380, 4)
821 #define SD_SW_STATUS_FUN_GRP1_RC(status) \
822  SD_SW_STATUS_STRUCTURE(status, 376, 4)
823 #define SD_SW_STATUS_FUN_GRP_RC_ERROR 0xFU
824 #define SD_SW_STATUS_DATA_STRUCT_VER(status) \
825  SD_SW_STATUS_STRUCTURE(status, 368, 8)
826 #define SD_SW_STATUS_FUN_GRP6_BUSY(status) \
827  SD_SW_STATUS_STRUCTURE(status, 352, 16)
828 #define SD_SW_STATUS_FUN_GRP5_BUSY(status) \
829  SD_SW_STATUS_STRUCTURE(status, 336, 16)
830 #define SD_SW_STATUS_FUN_GRP4_BUSY(status) \
831  SD_SW_STATUS_STRUCTURE(status, 320, 16)
832 #define SD_SW_STATUS_FUN_GRP3_BUSY(status) \
833  SD_SW_STATUS_STRUCTURE(status, 304, 16)
834 #define SD_SW_STATUS_FUN_GRP2_BUSY(status) \
835  SD_SW_STATUS_STRUCTURE(status, 288, 16)
836 #define SD_SW_STATUS_FUN_GRP1_BUSY(status) \
837  SD_SW_STATUS_STRUCTURE(status, 272, 16)
838 
842 #define CARD_STATUS_APP_CMD (1lu << 5)
843 #define CARD_STATUS_SWITCH_ERROR (1lu << 7)
844 #define CARD_STATUS_READY_FOR_DATA (1lu << 8)
845 #define CARD_STATUS_STATE_IDLE (0lu << 9)
846 #define CARD_STATUS_STATE_READY (1lu << 9)
847 #define CARD_STATUS_STATE_IDENT (2lu << 9)
848 #define CARD_STATUS_STATE_STBY (3lu << 9)
849 #define CARD_STATUS_STATE_TRAN (4lu << 9)
850 #define CARD_STATUS_STATE_DATA (5lu << 9)
851 #define CARD_STATUS_STATE_RCV (6lu << 9)
852 #define CARD_STATUS_STATE_PRG (7lu << 9)
853 #define CARD_STATUS_STATE_DIS (8lu << 9)
854 #define CARD_STATUS_STATE (0xFlu << 9)
855 #define CARD_STATUS_ERASE_RESET (1lu << 13)
856 #define CARD_STATUS_WP_ERASE_SKIP (1lu << 15)
857 #define CARD_STATUS_CIDCSD_OVERWRITE (1lu << 16)
858 #define CARD_STATUS_OVERRUN (1lu << 17)
859 #define CARD_STATUS_UNERRUN (1lu << 18)
860 #define CARD_STATUS_ERROR (1lu << 19)
861 #define CARD_STATUS_CC_ERROR (1lu << 20)
862 #define CARD_STATUS_CARD_ECC_FAILED (1lu << 21)
863 #define CARD_STATUS_ILLEGAL_COMMAND (1lu << 22)
864 #define CARD_STATUS_COM_CRC_ERROR (1lu << 23)
865 #define CARD_STATUS_UNLOCK_FAILED (1lu << 24)
866 #define CARD_STATUS_CARD_IS_LOCKED (1lu << 25)
867 #define CARD_STATUS_WP_VIOLATION (1lu << 26)
868 #define CARD_STATUS_ERASE_PARAM (1lu << 27)
869 #define CARD_STATUS_ERASE_SEQ_ERROR (1lu << 28)
870 #define CARD_STATUS_BLOCK_LEN_ERROR (1lu << 29)
871 #define CARD_STATUS_ADDRESS_MISALIGN (1lu << 30)
872 #define CARD_STATUS_ADDR_OUT_OF_RANGE (1lu << 31)
873 
874 #define CARD_STATUS_ERR_RD_WR (CARD_STATUS_ADDR_OUT_OF_RANGE \
875  | CARD_STATUS_ADDRESS_MISALIGN \
876  | CARD_STATUS_BLOCK_LEN_ERROR \
877  | CARD_STATUS_WP_VIOLATION \
878  | CARD_STATUS_ILLEGAL_COMMAND \
879  | CARD_STATUS_CC_ERROR \
880  | CARD_STATUS_ERROR)
881 
885 #define SD_STATUS_BSIZE (512 / 8)
886 
888 #define EXT_CSD_BSIZE 512
891 /* Below belongs to Properties Segment */
892 #define EXT_CSD_S_CMD_SET_INDEX 504lu
893 #define EXT_CSD_BOOT_INFO_INDEX 228lu
894 #define EXT_CSD_BOOT_SIZE_MULTI_INDEX 226lu
895 #define EXT_CSD_ACC_SIZE_INDEX 225lu
896 #define EXT_CSD_HC_ERASE_GRP_SIZE_INDEX 224lu
897 #define EXT_CSD_ERASE_TIMEOUT_MULT_INDEX 223lu
898 #define EXT_CSD_REL_WR_SEC_C_INDEX 222lu
899 #define EXT_CSD_HC_WP_GRP_SIZE_INDEX 221lu
900 #define EXT_CSD_S_C_VCC_INDEX 220lu
901 #define EXT_CSD_S_C_VCCQ_INDEX 219lu
902 #define EXT_CSD_S_A_TIMEOUT_INDEX 217lu
903 #define EXT_CSD_SEC_COUNT_INDEX 212lu
904 #define EXT_CSD_MIN_PERF_W_8_52_INDEX 210lu
905 #define EXT_CSD_MIN_PERF_R_8_52_INDEX 209lu
906 #define EXT_CSD_MIN_PERF_W_8_26_4_52_INDEX 208lu
907 #define EXT_CSD_MIN_PERF_R_8_26_4_52_INDEX 207lu
908 #define EXT_CSD_MIN_PERF_W_4_26_INDEX 206lu
909 #define EXT_CSD_MIN_PERF_R_4_26_INDEX 205lu
910 #define EXT_CSD_PWR_CL_26_360_INDEX 203lu
911 #define EXT_CSD_PWR_CL_52_360_INDEX 202lu
912 #define EXT_CSD_PWR_CL_26_195_INDEX 201lu
913 #define EXT_CSD_PWR_CL_52_195_INDEX 200lu
914 #define EXT_CSD_CARD_TYPE_INDEX 196lu
915 /* MMC card type */
916 # define MMC_CTYPE_26MHZ 0x1
917 # define MMC_CTYPE_52MHZ 0x2
918 #define EXT_CSD_CSD_STRUCTURE_INDEX 194lu
919 #define EXT_CSD_EXT_CSD_REV_INDEX 192lu
920 
921 /* Below belongs to Mode Segment */
922 #define EXT_CSD_CMD_SET_INDEX 191lu
923 #define EXT_CSD_CMD_SET_REV_INDEX 189lu
924 #define EXT_CSD_POWER_CLASS_INDEX 187lu
925 #define EXT_CSD_HS_TIMING_INDEX 185lu
926 #define EXT_CSD_BUS_WIDTH_INDEX 183lu
927 #define EXT_CSD_ERASED_MEM_CONT_INDEX 181lu
928 #define EXT_CSD_BOOT_CONFIG_INDEX 179lu
929 #define EXT_CSD_BOOT_BUS_WIDTH_INDEX 177lu
930 #define EXT_CSD_ERASE_GROUP_DEF_INDEX 175lu
931 
934 
937 
939 #define SPI_CMD_ENCODE(x) (0x40 | (x & 0x3F))
940 
944 #define R1_SPI_IDLE (1lu << 0)
945 #define R1_SPI_ERASE_RESET (1lu << 1)
946 #define R1_SPI_ILLEGAL_COMMAND (1lu << 2)
947 #define R1_SPI_COM_CRC (1lu << 3)
948 #define R1_SPI_ERASE_SEQ (1lu << 4)
949 #define R1_SPI_ADDRESS (1lu << 5)
950 #define R1_SPI_PARAMETER (1lu << 6)
951 // R1 bit 7 is always zero, reuse this bit for error
952 #define R1_SPI_ERROR (1lu << 7)
953 
958 #define R2_SPI_CARD_LOCKED (1lu << 0)
959 #define R2_SPI_WP_ERASE_SKIP (1lu << 1)
960 #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
961 #define R2_SPI_ERROR (1lu << 2)
962 #define R2_SPI_CC_ERROR (1lu << 3)
963 #define R2_SPI_CARD_ECC_ERROR (1lu << 4)
964 #define R2_SPI_WP_VIOLATION (1lu << 5)
965 #define R2_SPI_ERASE_PARAM (1lu << 6)
966 #define R2_SPI_OUT_OF_RANGE (1lu << 7)
967 #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
968 
974 #define SPI_TOKEN_SINGLE_MULTI_READ 0xFE
975 #define SPI_TOKEN_DATA_ERROR_VALID(token) (((token) & 0xF0) == 0)
976 #define SPI_TOKEN_DATA_ERROR_ERRORS (0x0F)
977 #define SPI_TOKEN_DATA_ERROR_ERROR (1lu << 0)
978 #define SPI_TOKEN_DATA_ERROR_CC_ERROR (1lu << 1)
979 #define SPI_TOKEN_DATA_ERROR_ECC_ERROR (1lu << 2)
980 #define SPI_TOKEN_DATA_ERROR_OUT_RANGE (1lu << 3)
981 #define SPI_TOKEN_SINGLE_WRITE 0xFE
985 #define SPI_TOKEN_MULTI_WRITE 0xFC
986 #define SPI_TOKEN_STOP_TRAN 0xFD
987 #define SPI_TOKEN_DATA_RESP_VALID(token) \
988  ((((token) & (1 << 4)) == 0) && (((token) & (1 << 0)) == 1))
989 #define SPI_TOKEN_DATA_RESP_CODE(token) ((token) & 0x1E)
990 #define SPI_TOKEN_DATA_RESP_ACCEPTED (2lu << 1)
991 #define SPI_TOKEN_DATA_RESP_CRC_ERR (5lu << 1)
992 #define SPI_TOKEN_DATA_RESP_WRITE_ERR (6lu << 1)
993 
997 
999 
1000 #ifdef __cplusplus
1001 }
1002 #endif
1003 
1004 #endif /* SD_MMC_PROTOCOL_H_INCLUDED */
SD/MMC protocol definitions.
uint32_t sdmmc_cmd_def_t
Value to define a SD/MMC/SDIO command.